Careers

PerfectVIPs is a leading Semiconductor company, providing ASIC Design and Verification Services, headquartered in California, USA with design centers in Bangalore, Bhubaneshwar and Ahmedabad in India. We offer Design and Verification Services which includes Micro-architecture development, RTL coding, Synthesis, developing custom and standard VIPs, Verification environment development and functional verification using both conventional and advanced techniques.

Our mission is to render long term, high quality Semiconductor ASIC Design and Verification services providing highest degree of customer satisfaction. We aim to understand comprehensive requirements of clients and to meet these requirements through dedicated efforts. Our vision is to serve our clients globally with commitment to quality and excellence by providing high quality services.

Current Openings

Specification Developer

Roles & Responsibilities

  • Senior Technical Specialist - must have the strong architecture and technical skills to understand and propose technical specification well
  • Key domain expert on Application development, Cloud, Networking, Security, Audio and Video
    • Any working experience as a subject matter expert in any of the domain above would be an advantage
    • Ability to do literature survey, essential research and elicitation methodologies would be helpful to perform this role.
  • Should be able to Visualize ‘expected’ scope/requirementsfrom the functional scope and develop technical requirements
    • Must contribute to all stages of Technical specification development such as elicitation, analysis, definition and spec writing
    • Identify and establish performance, safety, reliability, security and privacy requirements
  • Should be able to propose, Develop and Prototype improvedmechanism against the problems in the current specification.
    • Review existing specifications, define goals and expectations
    • Understand best practices, also bring in peer standards establishing industry contact
    • Perform essential research and outline supporting material
    • Develop/reuse new/existing standards
  • Must have good documentation skills
    • Ability to write the specifications clearly. Ability to deliver high quality documentation paying attention to detail.
    • Create and maintain the information architecture
    • Produce high-quality documentation that meets applicable standards and is appropriate for its intended audience.
    • Ability to quickly grasp complex technical concepts and make them easily understandable in text and pictures
    • Imagination to visualize elements or process as graphs/charts/illustrations.
    • Ability to create workflows/data flows/ state transition charts etc., using standard model techniques
  • Must have good communication skills
    • to interact with various stakeholders across industries and globally
    • work with internal teams to share an in-depth understanding of the technical details.
    • Any exposure in Standardization practices, draft preparation, development, working group participation, proposal writing would be a great add-on.

Skills Required

  • Knowledge of video, audio, aux sensors
  • Networking protocols (HTTP, MQTT, JSON, TCP…)
  • Cloud servers, Web servers
  • Security related technologies like JWS/JWE/X.509
  • Standardization of the specifications
  • Knowledge and working experience on Networking protocols (HTTP, MQTT, JSON, TCP…)
  • Knowledge and hands-on with security related technologies like JWS/JWE/X.509
  • Knowledge and working experience with Cloud servers, Web servers
  • Better to have familiarity with the multimedia format for video, audio, aux sensors
  • Better to have familiarity with the standardization of the specifications.
  • Good to have some exposure to IETF/IEEE or any standardization activities
  • Fair understanding of Open Source Software
  • Knowledge of standardization requirements/awareness

Experience
13 to 16 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bangalore, India

Apply now
C++ Developer - Media Applications

Roles & Responsibilities

  • Experienced C++ developer for a team that develops application software (UI and backend) at Sony India Software Center, Bangalore
  • Responsible for requirement analysis, design, implementation, developer testing and bug fixing of various modules
  • Interaction with global teams spread across Japan and North America

Key Qualifications

  • 4-6 years of work experience
  • Minimum 3 years of hands-on experience doing application and/or middleware design and development using C++
  • Bachelor's or Master's Degree in Computer Science or related field

Skills Required

  • Design patterns
  • C++ Developer
  • OOPS concepts
  • Design Principles
  • Data structures
  • Exposure to cross platform application development (windows, mac)
  • Familiar with concepts of C++ version 11
  • Experience in implementing UI using QML
  • Familiar with basic video concepts like bitrates, resolutions, video file formats, etc
  • Capable of resolving complex technical issues
  • Exposure of working in a scrum team
  • Excellent interpersonal and leadership skills
  • Excellent written and verbal communication skills

Experience
4 to 6 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bangalore, India

Apply now
Python/CI-CD DevOps Lead

Skills Required

  • Linux Administration
  • Linux Application development
  • AWS/Azure
  • DevOps Skills
  • CUSTOMER INTERACTION
  • GIT
  • Jenkins
  • Python development
  • Hands on Python scripting
  • Good communication skills
  • Working experience on production servers
  • Jenkins
  • Linux (system administration)
  • Git
  • AWS/Azure
  • Experience in interaction with customer.

Other Skills(good to have)

  • Docker
  • Ansible
  • Shell Scripting

Experience
5 to 7 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bangalore, India

Apply now
Lead Engineer -DevOps

Required Skills

  • Linux Administration
  • AWS/Azure
  • Git/Gerrit
  • Jenkins, Automation
  • Devops Engineer
  • Python advance
  • Hands on Python scripting (must)
  • Good communication skills
  • Working experience on production servers
  • Jenkins
  • Linux (system administration)
  • Git
  • AWS/Azure
  • Experience in interaction with customer

Other Skills(good to have)

  • Ansible
  • Shell Scripting

Experience
4 to 6 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bangalore, India

Apply now
Sr. DFT Engineer

Roles & Responsibilities

  • Implement modern DFT solutions for leading edge ICs on latest technology nodes, including implement the DFT architecture.
  • Work with RTL, custom digital/analog, verification, physical implementation, and timing teams during this DFT implementation.
  • Set-up, run, and debug block-level, SOC-level as well as full-chip ATPG (Automatic Test Pattern Generation) runs.
  • Deliver bring-up of test patterns and features post tape-out.
  • Manage DFT design flow infrastructure to lead to a successful DFT implementation.
  • Provide adapt off-the-shelf capabilities to build necessary CAD solutions.
  • Develop test automation solutions for Design-for-Test (DFT) insertion and verification.
  • Perform CAD development of the design methodology of memory build in self-test (MBIST).
  • Build the DFT implementation flow infrastructure, coordinate and support its deployment.

Key Qualifications

  • Bachelor's or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field and five (5) years of experience in the job offered or related occupation.
  • Experience must include five (5) years involved in: DFT architecture and planning for complex multi-million gate SoCs in latest technology nodes; SCAN/ATPG, and MBIST for complex multi-million gate SoCs; Mentor Tessent tool flows and Synopsys DFT compiler flows; creating and maintaining the EDA tool flows using PERL/Shell scripting; Silicon bring-up experience of MBIST and SCAN; creating iJTAG structure in Verilog; Logic Synthesis and Static Timing Closure.

Experience
5 to 8 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
San Jose, CA, USA

Apply now
ASIC/SoC/IP Verification Engineer Lead

Roles & Responsibilities

  • ASIC/SOC/IP Verification plan definition, testbench environment development in SystemVerilog/UVM
  • Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level
  • Support of assertion and coverage-driven methodology
  • Develop test cases to verify functional operation of that the system level
  • Experience in PCIe or NVMe or UFS or SATA or SAS or Ethernet or AXI or DDR protocols
  • Communicate test progress, test results, and other relevant information to project lead
  • Test any new software to ensure integration into company system meets functional requirements, system compliance, and technical specifications
  • Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws
  • Code and functional coverage objects of different blocks
  • Manage a team of verification engineers to perform the above tasks

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India
San Jose, USA

Apply now
Senior/Junior Verification Engineer

Roles & Responsibilities

  • Work as part of a dynamic, motivated, hardworking team
  • Leading the verification team delivering end to end verification, handling block and full-chip verification of complex SoCs
  • Your responsibilities may include Verification environment development, Test cases development, Function and code Coverage Analysis, software integration, etc.
  • You may also work on Verification IP development or IP Verification activities

Required Skills

  • Strong technical fundamentals with superior analytical and problem solving skills, familiarity with OOPs and scripting languages
  • Very strong proficiency in HVLs and HDLs (SystemVerilog, Verilog, VHDL, etc.)
  • Prior expertise with UVM based test bench with assertion is a big plus
  • Working experience in functional coverage and constrained random testing
  • Expertise in verification of protocols like Ethernet, PCIe, AXI, MIPI, SATA, USB, SAS, DDR, etc.
  • ARM based SoC verification is a big plus
  • Good communication skills, both written and oral

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India

Apply now
ASIC Design Engineer (Lead/Senior/Junior RTL Design)

Roles & Responsibilities

  • Define micro architecture from datasheet or requirements document
  • Perform RTL-level design, Synthesis, STA, CDC and Lint for any digital logic
  • Perform module-level verification and lint checking
  • Interact with verification engineers for test plan review, coverage debug

Required Skills

  • B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 3-5 years in ASIC Design
  • Strong hands-on experience with Verilog RTL-level design, Synthesis, STA, CDC and Lint
  • Should be able to work independently once the design requirements are specified
  • Knowledge of standard interfaces viz., AXI, AHB, SAS, DDR, PCIe, Flash-Memory, OTN, I2C/SPI is a plus
  • Knowledge of Perl, and EDA tools for LEC, Synthesis is a plus
  • Must have good spoken and written communication skills
  • Collaborate well in a team
  • Lead will manage a team of engineers to perform the above tasks.

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India
San Jose, USA

Apply now
Emulation Engineer (Lead/Senior/Junior)

Roles & Responsibilities

  • ASIC/SOC RTL Model Building using Emulator Compiler with customer specific requirements and Debugging
  • Creating and maintaining scripts, config scripts for Emulation Model Building
  • Cleaning up, Generation of Libraries for Model Building, Creating and maintaining emulation top wrapper
  • Integrating of Transactors, Simulation & Emulation Specific files, Memory modules and other RTL modules
  • Running the simulation tests, generation of Firmware hex files to be loaded onto the Emulation models
  • Running the basic sanity checks for the model releases
  • Running and integrate new test cases on Emulation Model to improve the Integrity of the released emulation model
  • Analysing and finding root cause of the runtime errors in Emulation and providing solutions/fixes for the customer issues
  • Strong in UVM, System Verilog (10 years and above)
  • Writing C-based code for verification at SoC level
  • Analyze and debug simulation failures for SoC subsystems and SOC top level tests
  • Experienced in DDR, PCIE, AXI protocols
  • Familiar with emulation using Zebu/Palladium/Veloce
  • Strong interpersonal and communication skills
  • Lead will manage a team of engineers to perform the above tasks

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India
San Jose, USA

Apply now
Physical Design Engineer (Lead/Senior/Junior)

Roles & Responsibilities

  • Take complete ownership for implementation of Block level designs
  • Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
  • Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
  • Well versed with the Level timing closure (STA), Timing closure methodologies
  • Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
  • Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
  • Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
  • Well aware of place and route methodologies and hands on experience with timing convergence
  • Good communication skill to negotiate with top level for convergence
  • Lead will manage a team of engineers to perform the above tasks

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India
San Jose, USA

Apply now
Embedded Software (Lead/Senior/Junior)

Required

  • Candidate must have experience in Android Frame and Linux kernel

Key Qualifications

  • Android Platform Experience
  • Linux device driver expertise
  • Intel/ARM BSP experience
  • Good C programming experience
  • Automotive experience is preferred, but not mandatory
  • Android expertise is preferred
  • Good communication skills, both written and oral
  • Lead will manage a team of engineers to perform the above tasks

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru
Ahmedabad
Bhubaneswar
Noida
Hyderabad
Pune
Onsite in India
San Jose, USA

Apply now
SoC Verification Engineer

Required Skills

  • SOC Verification plan definition, DV environment development in SV/UVM
  • Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level
  • Support of assertion and coverage-driven methodology
  • Develop test cases to verify functional operation of that the system level
  • Experience in PCIe or NVMe or UFS or DDR protocols
  • Communicate test progress, test results, and other relevant information to project lead
  • Test any new software to ensure integration into company system meets functional requirements, system compliance, and technical specifications
  • Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws
  • Code and functional coverage objects of different blocks

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Verification Engineer

Roles & Responsibilities

  • Work as part of a dynamic, motivated, hardworking team
  • Leading the verification team delivering end to end verification, handling block and full-chip verification of complex SoCs
  • Your responsibilities may include Verification environment development, Test cases development, Function and code Coverage Analysis, software integration, etc.
  • You may also work on Verification IP development or IP Verification activities

Required Skills

  • Strong technical fundamentals with superior analytical and problem solving skills, familiarity with OOPs and scripting languages
  • Very strong proficiency in HVLs and HDLs (SystemVerilog, Verilog, VHDL, etc.)
  • Prior expertise with OVM/UVM based test bench with assertion is a big plus.
  • Working experience in functional coverage and constrained random testing
  • Expertise in verification of protocols like Ethernet, PCIe, SATA, USB, SAS, DDR, etc.
  • ARM based SoC verification is a big plus
  • Good communication skills, both written and oral

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
ASIC Design Engineer (RTL Designer)

Roles & Responsibilities

  • Define micro architecture from datasheet or requirements document
  • Do RTL-level design for any digital logic
  • Perform module-level verification and lint checking
  • Interact with verification engineers for test plan review, coverage debug

Skills, Qualification and Experience

  • B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 3-5 years in ASIC Design
  • Strong hands-on experience with Verilog design
  • Should be able to work independently once the design requirements are specified
  • Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory, OTP, I2C/SPI is a plus
  • Knowledge of VP3, Perl, and EDA tools for LEC, Synthesis is a plus
  • Must have good spoken and written communication skills
  • Collaborate well in a team

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Emulation

Roles & Responsibilities

  • Strong in UVM, System Verilog (10 years and above)
  • Writing C-based code for verification at SoC level
  • Analyze and debug simulation failures for SoC subsystems and SOC top level tests
  • Experienced in DDR, PCIE, AXI protocols
  • Familiar with cadence simvision, and emulation using Palladium (preferred)
  • Strong interpersonal and communication skills

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Analog Mixed Signal IC Designer

Roles & Responsibilities

  • Seeking qualified circuit designers to work on the next generation analog & mixed-signal (AMS) circuit’s world-leading systems-on-chip (SOCs). You will be part of a growing AMS team involved in design and productization on leading-edge CMOS process technology nodes
  • Key Qualifications
  • Perform transistor-level feasibility study and modeling for various analog/mixed-signal circuit blocks
  • Designing blocks and documenting design simulation and verification towards formal design reviews
  • rive mask design to implement layout views of designs and drive layout reviews
  • Post-layout and top-level simulations to validate top-level integration
  • Run design verification flows (e.g., electro-migration, IR drop, LEC, timing, etc.) to verify design is ready for tape-out
  • Participating in production and bench-level test plans
  • Taking lab measurements to validate performance compliance with the spec
  • Participating in reviewing yield/lab test results to drive bug fixes

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Physical Design Engineer

Roles & Responsibilities

  • Take complete ownership for implementation of Block level designs
  • Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
  • Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
  • Well versed with the Level timing closure (STA), Timing closure methodologies
  • Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
  • Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
  • Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
  • Well aware of place and route methodologies and hands on experience with timing convergence
  • Good communication skill to negotiate with top level for convergence

Experience
2 to 12 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now