Careers

PerfectVIPs is a leading Semiconductor company, providing ASIC Design and Verification Services, headquartered in California, USA with design centers in Bangalore, Bhubaneshwar and Ahmedabad in India. We offer Design and Verification Services which includes Micro-architecture development, RTL coding, Synthesis, developing custom and standard VIPs, Verification environment development and functional verification using both conventional and advanced techniques.

Our mission of is to render long term, high quality Semiconductor ASIC Design and Verification services providing highest degree of customer satisfaction. We aim to understand comprehensive requirements of clients and to meet these requirements through dedicated efforts. Our vision is to serve our clients globally with commitment to quality and excellence by providing high quality services.

Current Openings

SoC Verification Engineer

Technical Skills Required

  • SOC Verification plan definition, DV environment development in SV/UVM
  • Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level
  • Support of assertion and coverage-driven methodology
  • Develop test cases to verify functional operation of that the system level
  • Experience in PCIe or NVMe or UFS or DDR protocols
  • Communicate test progress, test results, and other relevant information to project lead
  • Test any new software to ensure integration into company system meets functional requirements, system compliance, and technical specifications
  • Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws
  • Code and functional coverage objects of different blocks

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Verification Engineer

Roles & Responsibilities

  • Work as part of a dynamic, motivated, hardworking team
  • Leading the verification team delivering end to end verification, handling block and full-chip verification of complex SoCs
  • Your responsibilities may include Verification environment development, Test cases development, Function and code Coverage Analysis, software integration, etc.
  • You may also work on Verification IP development or IP Verification activities

Technical Skills Required

  • Strong technical fundamentals with superior analytical and problem solving skills, familiarity with OOPs and scripting languages
  • Very strong proficiency in HVLs and HDLs (SystemVerilog, Verilog, VHDL, etc.)
  • Prior expertise with OVM/UVM based test bench with assertion is a big plus.
  • Working experience in functional coverage and constrained random testing
  • Expertise in verification of protocols like Ethernet, PCIe, SATA, USB, SAS, DDR, etc.
  • ARM based SoC verification is a big plus
  • Good communication skills, both written and oral

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
ASIC Design Engineer (RTL Designer)

Roles & Responsibilities

  • Define micro architecture from datasheet or requirements document
  • Do RTL-level design for any digital logic
  • Perform module-level verification and lint checking
  • Interact with verification engineers for test plan review, coverage debug

Skills, Qualification and Experience

  • B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 3-5 years in ASIC Design
  • Strong hands-on experience with Verilog design
  • Should be able to work independently once the design requirements are specified
  • Knowledge of standard interfaces viz., AXI, AHB, Flash-Memory, OTP, I2C/SPI is a plus
  • Knowledge of VP3, Perl, and EDA tools for LEC, Synthesis is a plus
  • Must have good spoken and written communication skills
  • Collaborate well in a team

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Emulation

Roles & Responsibilities

  • Strong in UVM, System Verilog (10 years and above)
  • Writing C-based code for verification at SoC level
  • Analyze and debug simulation failures for SoC subsystems and SOC top level tests
  • Experienced in DDR, PCIE, AXI protocols
  • Familiar with cadence simvision, and emulation using Palladium (preferred)
  • Strong interpersonal and communication skills

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Analog Mixed Signal IC Designer

Roles & Responsibilities

  • Seeking qualified circuit designers to work on the next generation analog & mixed-signal (AMS) circuit’s world-leading systems-on-chip (SOCs). You will be part of a growing AMS team involved in design and productization on leading-edge CMOS process technology nodes
  • Key Qualifications
  • Perform transistor-level feasibility study and modeling for various analog/mixed-signal circuit blocks
  • Designing blocks and documenting design simulation and verification towards formal design reviews
  • rive mask design to implement layout views of designs and drive layout reviews
  • Post-layout and top-level simulations to validate top-level integration
  • Run design verification flows (e.g., electro-migration, IR drop, LEC, timing, etc.) to verify design is ready for tape-out
  • Participating in production and bench-level test plans
  • Taking lab measurements to validate performance compliance with the spec
  • Participating in reviewing yield/lab test results to drive bug fixes

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Physical Design Engineer

Roles & Responsibilities

  • Take complete ownership for implementation of Block level designs
  • Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
  • Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
  • Well versed with the Level timing closure (STA), Timing closure methodologies
  • Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
  • Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
  • Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
  • Well aware of place and route methodologies and hands on experience with timing convergence
  • Good communication skill to negotiate with top level for convergence

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now
Embedded Software

Required

  • Candidate with Android Frame and Linux kernel experience

Technical Skills Required

  • Android Platform Experience
  • Linux device driver expertise
  • Intel/ARM BSP experience
  • Good C programming experience
  • Automotive experience is preferred, but not mandatory
  • Android expertise is preferred
  • Good communication skills, both written and oral

Experience
2 to 12+ Years & above
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
Bengaluru, Ahmedabad, Bhubaneswar, Noida, Hyderabad, Pune, Onsite in India

Apply now