Packet Generators



NVM Express is a scalable host controller interface designed to address the needs of Enterprise, Data Center and Client systems for supporting chip-to-chip, board-to-board, adapter and distance solutions as shown in Figure 1. The protocol can efficiently use interconnect and fabric technologies such as PCI Express, Ethernet and Fiber Channel. This product provides traffic generator, protocol analysis, emulation, exerciser and other test equipment to service all NVMe storage applications.

As storage developers make the transition from legacy SAS and SATA protocol-based SSDs to the more advanced NVMe and SATA Express technologies, they are encountering limitations in available design and test tools including limited trace recording times and a lack of standardized analysis reports for PCIe-based storage.

  • No requirement for un-cacheable/MMIO register reads in the command submission or completion path
  • A maximum of 1 MMIO register write is necessary for the command submission path
  • Support for up to 65536 I/O queues, with each I/O supporting up to 64K outstanding commands
  • Priority associated with each I/O queue with a well-defined arbitration mechanism
  • All information to complete a 4KB read request is included in the 64B command itself, ensuring efficient small I/O operation
  • An official and streamlined command set
  • Support for MSI/MSI-X and interrupt aggregation
  • Efficient support for I/O virtualization architectures, such as SR-IOV
  • Robust error reporting and management capabilities
  • Support for multi-path I/O and namespace sharing
  • These methods can be used for verification of most complex hardware design to simple hardware design
  • Easy to use solution, plug and play type solutions
  • Software packet generators are very cost-effective solutions, they are cheaper compared to high license costing software products available in the market
  • Creates beautiful Emulation environment, which can mimic many simulation verification scenarios
  • Detect bug in Pre-silicon phase, which can save millions of dollars of re-spinning silicon cost
  • Post-silicon also software portion can be used for validation
  • Help to build a parallel structure to simulation to find more design bugs quickly
  • The overall runtime can be reduced to as much as 10 times than long SOC simulations. This can speed up TAPE OUT of the chip
  • Scoreboarding and traffic analysis can be done very well in the Software solution