Packet Generators



Packet Generator is a software tool that will be running on a Host computer and generate traffic patterns. PCIe packet generator is a product that generates series of Transaction Layer Packets (TLPs) which can be used by emulator platform to generate traffic on DUTs interfaces. Also, it can be used on Simulation platform to generate traffic on simulation environment on DUTs interface.

  • It works on three types of configuration modes: Memory Packet, Configuration Packet and I/O Packet (for legacy devices)
  • All PCIe Packet generation logic generates
    • 3DW header bits for Memory-Read (MRD) and MemoryWrite (MWR) with 32-bit addressing, Config-Read (CFGRD), Config-Write (CFGWR), I/O-Read (IORD), I/O-Write (IOWR)
    • 4DW header bits for Memory-Read (MRD), Memory-Write (MWR) with 64-bit addressing
  • The key aspects of the Transaction Layer are:
    • A pipelined full split-transaction protocol
    • Mechanisms for differentiating the ordering and processing requirements of TLPs
    • Credit-based flow control
    • Optional support for data poisoning and end-to-end data integrity detection
  • The above TLPs generated will pass through Datalink Layer and then to Physical Layer to finally generate a serial data stream. Physical layer have 2 sub blocks named logical and physical sub block
  • The Data Link Layer is responsible for reliably conveying Transaction Layer Packets (TLPs) supplied by the Transaction Layer across a PCI Express Link to the other component’s Transaction Layer. Services provided by the Data Link Layer include:
    • Data Exchange
    • Error Detection and Retry
    • Initialization and Power Management
  • The logical sub-block has two main sections: a Transmit section that prepa res outgoing information passed from the Data Link Layer for transmission by the electrical sub -block, and a Receiver section that identifies and prepares received information before passing it to the Data Link Layer.
  • PCI Express uses 8b/10b encoding when the data rate is 2.5 GT/s or 5.0 GT/s. For data rates greater than or equal to 8.0 GT/s, it uses a per-lane code along with physical layer encapsulation.
  • These methods can be used for verification of most complex hardware design to simple hardware design
  • Easy to use solution, plug and play type solutions
  • Software packet generators are very cost-effective solutions, they are cheaper compared to high license costing software products available in the market
  • Creates beautiful Emulation environment, which can mimic many simulation verification scenarios
  • Detect bug in Pre-silicon phase, which can save millions of dollars of re-spinning silicon cost
  • Post-silicon also software portion can be used for validation
  • Help to build a parallel structure to simulation to find more design bugs quickly
  • The overall runtime can be reduced to as much as 10 times than long SOC simulations. This can speed up TAPE OUT of the chip
  • Scoreboarding and traffic analysis can be done very well in the Software solution